Self-driven synchronous rectification scheme

ABSTRACT

A self-driven synchronous rectification circuit which includes two power switches S 1  and S 2 ; a transformer Tr having a primary winding N p , a secondary winding N S , and an auxiliary winding N a ; two secondary synchronous rectifiers S 3  and S 4 ; two diodes D 1 , and D 2 ; and two zener diodes ZD 1  and ZD 2 . The number of auxiliary winding turns N a  of the transformer Tr ensure that the synchronous rectifiers S 3  and S 4  are supplied with an adequate gate-drive voltage. When S 3  conducts, the gate-drive voltage of S 4  is clamped by D 1 . Likewise, when S 4  conducts, the gate-drive voltage of S 3  is clamped by D 2 . ZD 1  and ZD 2  operate to restrain the gate overvoltage of S 3  and S 4 , respectively. With this design, the self-driven synchronous rectifier circuit operates normally at various output voltages, such as low output voltages of 3.3V or lower and/or high output voltages above 6V.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a logic integrated circuit. In particular, the present invention relates to a self-driven, synchronous rectification scheme for a power converter which is easily adapted to various circuit topologies.

[0002] There is an ever-increasing demand in the power electronics market for low voltage and high current DC-DC converters. As output voltage is desired to be 3.3V or lower, even a state-of-the-art schottky diode with a forward voltage drop of 0.3V has an unacceptable amount of power loss.

[0003] Because of this, synchronous rectifiers are often used to improve the efficiency of DC-DC converters. Generally, there are two types of synchronous rectifiers, self-driven and externally driven. Since the self-driven mode is usually less complex, less costly and more reliable, it is preferred for use with most low voltage DC-DC converter applications.

[0004]FIG. 1A illustrates a conventional self-driven synchronous rectification, asymmetrical, zero voltage switching (ZVS) half-bridge (HB) topology. Although this circuit is very simple, it is only suitable for applications where the output voltage is in the range of from about 3.3V to 6V. Referring to FIG. 1B, the gate-drive voltages V_(gs3) and V_(vs4) of synchronous rectifiers S₃ and S₄, respectively, are as follows: $\begin{matrix} {V_{gs3} = {{\frac{2N_{s}}{N_{p}}{DV}_{in}} = {{\frac{2}{N}{DV}_{in}} = {\frac{V_{0}}{1 - D}\quad \left( {t_{0} \leq t \leq t_{1}} \right)}}}} & (1) \\ {V_{gs4} = {{\frac{2N_{s}}{N_{p}}\left( {1 - D} \right)V_{in}} = {{\frac{2\left( {1 - D} \right)}{N}V_{in}} = {\frac{V_{0}}{D}\quad \left( {t_{1} \leq t \leq t_{2}} \right)}}}} & (2) \end{matrix}$

[0005] wherein, V_(in) is the input voltage; V_(O) is the output voltage; D is the steady-state duty cycle; N_(p) is the number of primary winding turns of the transformer; N_(S) is the number of secondary turns of the transformer; and N is the turn ratio of the transformer. The turn ratio of the transformer TR is calculated by dividing the number of primary windings by the number of secondary windings (i.e. N=N_(p)/N_(S)).

[0006]FIG. 1B illustrates the switching waveform occurring in the converter illustrated in FIG. 1A. As shown in FIG. 1B, the gate-drive voltage V_(gs4) of S₄ is always higher than the gate-drive voltage V_(gs3) of S₃ if D is less than 50%. If we assume that the minimum steady-state duty cycle D at heavy load is 30%, then V_(gs3) is about 1.4V, and V_(gs4) is about 3.3V. Since most synchronous rectifiers (including logic level devices) only work well with the gate-drive voltage between about 4V and 20V, the circuit shown in FIG. 1A only works well when the output voltage V_(O) is between 2.9V to 6V. If the output voltage is below 2.9V, S₃ would be under driven. If the output voltage were about 6V, then S₄ would be over driven. In either case the synchronous rectifiers are easily rendered inoperative.

[0007] Accordingly, there remains a need for a self-driven synchronous rectifier which operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.

SUMMARY OF THE INVENTION

[0008] The self-driven synchronous rectification circuit of the present invention includes two power switches S₁ and S₂; a transformer Tr having a primary winding N_(p), a secondary winding N_(S) and an auxiliary winding N_(a); two secondary synchronous rectifiers S₃ and S₄; two diodes D₁ and D₂; and two zener diodes ZD₁ and ZD₂.

[0009] The number of auxiliary winding turns N_(a) of the transformer Tr ensure that the synchronous rectifiers S₃ and S₄ are supplied with an adequate gate-drive voltage. The selection of the number of auxiliary winding turns for use is determined according to the output voltage required. In the circuit of the present invention, when S₃ conducts, the gate-drive voltage of S₄ is clamped by D₁. Also, when S₄ conducts, the gate-drive voltage of S₃ is clamped by D₂. In other words, D₁ and D₂ prevent S₃ and S₄ from conducting at the same time. ZD₁ and ZD₂ restrain the gate overvoltage of S₃ and S₄, respectively.

[0010] With the above circuit configuration, a self-driven synchronous rectification scheme can be implemented which operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings, wherein:

[0012]FIG. 1A is a circuit diagram of conventional self-driven synchronous rectification, asymmetrical ZVS HB converter;

[0013]FIG. 1B illustrates the switching waveform occurring in the converter illustrated in FIG. 1A;

[0014]FIG. 2A is a circuit diagram of an asymmetrical ZVS HB converter which incorporates a self-driven synchronous rectifier circuit in accordance with the present invention;

[0015]FIG. 2B illustrates the switching waveform occurring in the converter of FIG. 2A;

[0016]FIG. 3 is a circuit diagram showing the self-driven synchronous rectifier circuit of the present invention applied to a forward converter; and

[0017]FIG. 4 is a circuit diagram showing the self-driven synchronous rectifier circuit of the present invention applied to a full-bridge converter.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0018] Referring now to the drawings, FIG. 2A shows a circuit diagram of an asymmetrical ZVS HB converter incorporating the self-driven synchronous rectifier circuit of the present invention. The self-driven synchronous rectifier circuit of the present invention includes two power switches S₁ and S₂; a transformer Tr having a primary winding N_(p), a secondary winding N_(S) and an auxiliary winding N_(a); two secondary synchronous rectifiers S₃ and S₄; two diodes D₁ and D₂; and two zener diodes ZD₁ and ZD_(2.)

[0019] The number of auxiliary winding turns N_(a) of the transformer Tr ensure that the synchronous rectifiers S₃ and S₄ are supplied with an adequate gate-drive voltage. The selection of the number of auxiliary winding turns for use is determined according to the output voltage required. Such a determination will be evident to one of ordinary skill in the art, and will depend upon, for example, the wire size chosen and the inductance required of the winding. In the circuit of the present invention, when S₃ conducts, the gate-drive voltage of S₄ is clamped by D₁. Also, when S₄ conducts, the gate-drive voltage of S₃ is clamped by D₂. In other words, D₁ and D₂ prevent S₃ and S₄ from conducting at the same time. ZD₁ and ZD₂ operate to restrain the gate overvoltage of S₃ and S₄, respectively. Because of this circuit configuration, the self-driven synchronous rectifier circuit operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.

[0020]FIG. 2B illustrates the switching waveform of the converter shown in FIG. 2A. V_(gs1), and V_(gs2) represent the gate voltage waveforms of the two power switches S₁ and S₂. VP is the primary voltage waveform of transformer Tr. V_(Na) is the voltage waveform of the auxiliary winding. V_(gs3) and V_(gs4) represent the gate voltage waveforms of the two synchronous rectifiers S₃ and S₄. V_(gs3) and V_(gs4) are calculated as follows: $\begin{matrix} {V_{gs3} = {\frac{N_{a}}{N_{p}}{DV}_{in}\quad \left( {t_{0} \leq t \leq t_{1}} \right)}} & (3) \\ {V_{gs4} = {\frac{N_{a}}{N_{p}}\left( {1 - D} \right)V_{in}\quad \left( {t_{1} \leq t \leq t_{2}} \right)}} & (4) \end{matrix}$

[0021] wherein, D is the on-time of switch S₁ in percent duty cycle; 1-D is the on-time of switch S₂ in percent duty cycle; N_(p) is the number of primary winding turns of transformer Tr; N_(a) is the number of auxiliary winding turns of the transformer Tr; and V_(in) is the input voltage.

[0022] Comparing equations (3) and (4) above with equations (1) and (2), it can be seen that, while the input voltage V_(in), the duty cycle D and the primary and secondary turns of the transformer (N_(p), N_(S)) are determined, the gate voltage of self-driven synchronous rectifiers S₃ and S₄ is adjusted by selecting the number of auxiliary winding turns N_(a) of transformer Tr. This selection of the auxiliary number of winding turns N_(a) ensures a reasonable gate-drive voltage for the synchronous rectifiers S₃ and S₄ even when the output voltage is lower than 2.9V or higher than 6V.

[0023] The principle of operation is as follows. Referring to FIG. 2B, during time t₀-t₁, S₂ and S₃ are on, and S₁ and S₄ are off. The primary voltage of transformer Tr is DV_(in). Accordingly, the voltage of the auxiliary winding V_(Na), namely the gate-drive voltage V_(gs3) of S₃ is as follows: $\frac{N_{a}}{N_{p}}{DV}_{in}$

[0024] When S₃ is on, the gate-drive voltage V_(gs4) of S4 is clamped to zero through the diode D₁ so as to prevent S₃ and S₄ from conducting at the sane time. At time t₁, S₂ is turned off and S₁ is turned on. When S₁ is turned on, the voltage of the primary winding of transformer N_(p) reverses and the voltages of the secondary winding N_(S). and auxiliary winding N_(a) also reverse. When the voltages of the windings reverse, S₄ is turned on and S₃ is turned off. During this interval, the gate-drive voltage V_(gs4) of S₄ is as follows: $\frac{N_{a}}{N_{p}}\left( {1 - D} \right)V_{in}$

[0025] When S₄ is on, the gate-drive voltage of S₃ is clamped to zero through the diode D₂ so as to prevent S₃ and S₄ from conducting at the same time. The function of ZD₁ and ZD₂ is to restrain the gate overvoltage of each of the synchronous rectifiers S₃ and S₄, respectively.

[0026] While the embodiment of the invention described above is presently preferred, many variations and modifications are possible depending on practical needs.

[0027] For example, the self-driven synchronous rectifier circuit of the present invention can be applied to a symmetrical HB converter. With the proper adjustments, which are well within the level of one of ordinary skill in the art given the present disclosure, the self-driven synchronous rectifier circuit can also be applied to a ZVS HB converter whose duty cycle is close to 50%.

[0028] In addition to an asymmetrical and a symmetrical HB converter, the self-driven synchronous rectifier circuit of the present invention can be applied to a forward converter, such as that shown in FIG. 3, and a full-bridge converter, such as that shown in FIG. 4.

[0029] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims. 

What is claimed is:
 1. A self-driven synchronous rectifier circuit, comprising: an input terminal for receiving a voltage; a first power switch electrically connected to the input terminal; a second power switch electrically connected to the input terminal; a transformer connected to the first power switch and the second power switch, the transformer including a primary winding, a secondary winding and an auxiliary winding; a first synchronous rectifier connected to the first power switch via the transformer; a second synchronous rectifier connected to the second power switch via the transformer; a first diode connected to the second synchronous rectifier; and a second diode connected to the first synchronous rectifier, wherein the first and second diodes are operable to prevent the first and second synchronous rectifiers from conducting at the same time.
 2. The self-driven synchronous rectifier circuit according to claim 1, wherein the gate drive voltage of the second synchronous rectifier is clamped by the first diode when the first synchronous rectifier conducts.
 3. The self-driven synchronous rectifier circuit according to claim 2, wherein the gate drive voltage of the first synchronous rectifier is clamped by the second diode when the second synchronous rectifier conducts.
 4. The self-driven synchronous rectifier circuit according to claim 1, wherein the auxiliary winding ensures that the first and second synchronous rectifiers are supplied with an adequate gate-drive voltage.
 5. The self-driven synchronous rectifier circuit according to claim 4, wherein the gate voltages of the first synchronous rectifier and the second synchronous rectifier are adjusted by selecting the number of turns of the auxiliary winding.
 6. The self-driven synchronous rectifier circuit according to claim 1, wherein the self driven synchronous rectifier circuit is operable at output voltages from below 2.9V to output voltages above 6V.
 7. The self-driven synchronous rectifier circuit according to claim 1, a voltage across the primary winding, a voltage across the secondary winding and a voltage across the auxiliary winding are reversed relative to the turning on of the first switch and the second switch.
 8. The self-driven synchronous rectifier circuit according to claim 1, further comprising: a third diode connected to the second synchronous rectifier; and a fourth diode connected to the first synchronous rectifier, the third diode operating to restrain gate overvoltage of the first synchronous rectifier, the fourth diode operating to restrain gate overvoltage of the second synchronous rectifier.
 9. The self-driven synchronous rectifier circuit according to claim 8, wherein the third and fourth diodes are zener diodes.
 10. A method of self-driving a synchronous rectifier circuit, the method comprising: during a first part of a cycle: (1) turning a first synchronous rectifier on; (2) turning a second synchronous rectifier off such that the first and second synchronous rectifiers do not conduct at the same time, during a second part of the cycle: (3) turning on the second synchronous rectifier; (4) turning off the first synchronous rectifier such that the first and second synchronous rectifiers do not conduct at the same time; and (5) reversing a voltage across a transformer in response to the turning on and turning off of the first and second synchronous rectifiers.
 11. The method of self-driving a synchronous rectifier circuit according to claim 10, further comprising adjusting a gate voltage of the first and second synchronous rectifiers by selecting a number of turns of an auxiliary winding of the transformer.
 12. The method of self-driving a synchronous rectifier circuit according to claim 10, wherein the second synchronous rectifier is turned off by clamping the second synchronous rectifier's gate drive voltage to zero.
 13. The method of self-driving a synchronous rectifier circuit according to claim 12, wherein the gate drive voltage is clamped to zero using a diode.
 14. The method of self-driving a synchronous rectifier circuit according to claim 10, wherein the first synchronous rectifier is turned off by clamping the first synchronous rectifier's gate drive voltage to zero.
 15. The method of self-driving a synchronous rectifier circuit according to claim 14, wherein the gate drive voltage is clamped to zero using a diode.
 16. The method of self-driving a synchronous rectifier circuit according to claim 10, further comprising restraining gate overvoltage of the first and second synchronous rectifiers.
 17. The method of self-driving a synchronous rectifier circuit according to claim 16, wherein the gate overvoltage of the first synchronous rectifier is restrained by a first zener diode.
 18. The method of self-driving a synchronous rectifier circuit according to claim 17, wherein the gate overvoltage of the second synchronous rectifier is restrained by a second zener diode. 